1. Field of the Invention
The present invention relates to a method for driving a semiconductor device including a selection circuit and an electronic device including the semiconductor device.
2. Description of the Related Art
In an integrated circuit, a multiplexer is used as a selection circuit for selecting an input signal, for example. The multiplexer is a circuit for outputting one output signal from a plurality of input signals. Here, a reconfigurable logic circuit is described as an example of a semiconductor device including multiplexers.
The reconfigurable logic circuit includes a plurality of logic blocks each including a plurality of logic elements, a plurality of wirings for connecting the logic blocks, a programmable switch, and an input/output block.
The reconfigurable logic circuit can have a logical structure with a high degree of flexibility by changing the function of each logic element or connecting the logic blocks between the wirings. For example, in general, an output of a look-up table in a logic element is selected by a multiplexer to change the logic of the logic element. In that case, the multiplexer has not only a system in which its operation depends on a signal input from the outside but also a system in which its operation depends on data stored in a memory in advance. A circuit including such a memory and a multiplexer is referred to as a programmable multiplexer (see Patent Document 1).
Here, a typical multiplexer structure as disclosed in Patent Document 2 will be described. FIG. 12A shows a two-input and one-output multiplexer including a static random access memory (SRAM), a transistor T11, and a transistor T12. Each of the transistors T11 and T12 controls conduction between an input terminal and an output terminal and is also referred to as a transfer gate. In the transistor T11, one of a source and a drain is connected to an input terminal IN_A, the other of the source and the drain is connected to an output terminal OUT, and a gate is connected to a terminal D of the SRAM. In the transistor T12, one of a source and a drain is connected to an input terminal IN_B, the other of the source and the drain is connected to the output terminal OUT, and a gate is connected to a terminal DB of the SRAM. One of a signal input into the input terminal IN_A and a signal input into the input terminal IN_B is output from the output terminal OUT in accordance with a combination of logic values of selection signals which are held in the SRAM and are output from the terminal D and the terminal DB.
However, in the case where the transistors T11 and T12 are n-channel transistors, a potential of a signal output from the transistor T11 or T12 to the output terminal OUT is lower than one of the potentials of the signals input into the input terminal IN_A and the input terminal IN_B by a threshold voltage of the transistor T11 or T12.
Therefore, it is necessary to make the potential of the terminal D or DB higher than maximum potentials of a signal input into the input terminal IN_A and a signal input into the input terminal IN_B by the threshold voltages or more. This means to increase the power source voltage of the SRAM.
For example, in the case where the maximum potentials of the signals input into the input terminal IN_A and the input terminal IN_B are each +1 V and the threshold voltages of the transistor T11 and the transistor T12 are each +0.5 V, it is necessary to make the potential of the terminal D or DB higher than or equal to +1.5 V. However, in the case where high-speed operation (here, a reduction in the resistance of the multiplexer) is necessary, the potential of the terminal D or DB needs to be higher than or equal to +1.6 V, preferably higher than or equal to +1.7 V. Therefore, the potential of a high-potential node of the SRAM needs to be higher than or equal to +1.6 V, preferably higher than or equal to +1.7 V.
Thus, as shown in FIG. 12B, a method for suppressing change in potential of an output signal from an input signal by using a transmission gate TG1 and a transmission gate TG2 instead of the transistors T11 and T12 is employed.